? semiconductor components industries, llc, 2006 june, 2006 ? rev. 6 1 publication order number: 74fst6800/d 74fst6800 10?bit bus switch with precharged outputs the on semiconductor 74fst6800 is a 10 ? bit bus switch with precharged outputs. the device is cmos ttl compatible when operating between 4.0 and 5.5 volts. the device exhibits extremely low r on and adds nearly zero propagation delay. the device adds no noise or ground bounce to the system. features ? r on 4 typical ? less than 0.25 ns ? max delay through switch ? nearly zero standby current ? no circuit bounce ? control inputs are ttl/cmos compatible ? pin ? for ? pin compatible with qs6800, fst6800, cbt6800 ? all popular packages: soic ? 24, tssop ? 24, qsop ? 24 ? all devices in package tssop are inherently pb ? free* figure 1. 24 ? lead pinout truth table function a 0 ? a 9 b 0 ? b 9 connect 1 2 3 4 5 6 7 8 9 10 11 12 v cc b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 biasv 24 23 22 21 20 19 18 17 16 15 14 13 oe a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 gnd bias v precharge note: h = high voltage level l = low voltage level l oe h *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. a = assembly location l, wl = wafer lot y, yy = year w, ww = work week tssop ? 24 dt suffix case 948h 24 1 qsop ? 24 qs suffix case 492b soic ? 24 dw suffix case 751e 24 1 1 24 fst6800 awlyww marking diagrams 24 1 24 1 1 24 fst 6800 alyw fst6800 awlyyww description pin names oe a pin bus switch enable bus a b bus b see detailed ordering and shipping information in the package dimensions sect ion on page 2 of this data sheet. ordering information http://onsemi.com
74fst6800 http://onsemi.com 2 figure 2. logic diagram 1 11 2 oe a 9 a 0 23 14 b 9 b 0 13 bias v ordering information device order number package shipping ? 74fst6800dw soic ? 24 48 units / rail 74FST6800DWR2 soic ? 24 2500 units / tape & reel 74fst6800dt tssop ? 24* (pb ? free) 96 units / rail 74fst6800dtr2 tssop ? 24* (pb ? free) 2500 units / tape & reel 74fst6800qs qsop ? 24 96 units / rail 74fst6800qsr qsop ? 24 2500 units / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb ? free. maximum ratings symbol parameter value unit v cc dc supply voltage 0.5 to 7.0 v v i dc input voltage 0.5 to 7.0 v v o dc output voltage 0.5 to 7.0 v i ik dc input diode current v i gnd 50 ma i ok dc output diode current v o gnd 50 ma i o dc output sink current 128 ma i cc dc supply current per supply pin 100 ma i gnd dc ground current per ground pin 100 ma t stg storage temperature range 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c ja thermal resistance soic tssop qsop 125 170 200 c/w msl moisture sensitivity level 1 f r flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in v esd esd withstand voltage human body model (note 1) machine model (note 2) charged device model (note 3) 2000 200 n/a v i latchup latchup performance above v cc and below gnd at 85 c (note 4) 500 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. tested to eia/jesd22 ? a114 ? a. 2. tested to eia/jesd22 ? a115 ? a. 3. tested to jesd22 ? c101 ? a. 4. tested to eia/jesd78.
74fst6800 http://onsemi.com 3 recommended operating conditions symbol parameter min max unit v cc supply voltage operating, data retention only 4.0 5.5 v v i input voltage (note 5) 0 5.5 v v o output voltage (high or low state) 0 5.5 v t a operating free ? air temperature 40 85 c t/ v input transition rise or fall rate switch control input switch i/o v cc = 5.0 v 0.5 v 0 dc 5 ns/v 5. unused control inputs may not be left open. all control inputs must be tied to a high or low logic input voltage level. dc electrical characteristics symbol parameter conditions v cc (v) t a = 40 c to 85 c unit min typ* max v ik clamp diode resistance i in = 18ma 4.5 1.2 v v ih high ? level input voltage 4.0 to 5.5 2.0 v v il low ? level input voltage 4.0 to 5.5 0.8 v i i input leakage current 0 v in 5.5 v 5.5 1.0 a i oz off ? state leakage current 0 a, b v cc 5.5 1.0 a r on switch on resistance (note 6) v in = 0 v, i in = 64 ma 4.5 4 7 v in = 0 v, i in = 30 ma 4.5 4 7 v in = 2.4 v, i in = 15 ma 4.5 8 15 v in = 2.4 v, i in = 15 ma 4.0 11 20 i cc quiescent supply current v in = v cc or gnd, i out = 0 5.5 3 a i cc increase in i cc per input one input at 3.4 v, other inputs at v cc or gnd 5.5 2.5 ma *typical values are at v cc = 5.0 v and t a = 25 c. 6. measured by the voltage drop between a and b pins at the indicated current through the switch. on resistance is determined by the lower of the voltages on the two (a or b) pins. ac electrical characteristics symbol parameter conditions t a = 40 c to 85 c c l = 50 pf, ru = rd = 500 unit v cc = 4.5 ? 5.5 v v cc = 4.0 v min max min max t phl , t plh prop delay bus to bus (note 7) v i = open 0.25 0.25 ns t pzh , t pzl output enable time, i oe to bus a, b bias v = gnd v i = open for t pzh 1.0 5.1 5.6 ns t phz , t plz output disable time, i oe to bus a, b bias v = gnd v i = open for t phz 1.0 5.5 5.5 ns 7. this parameter is guaranteed by design but is not tested. the bus switch contributes no propagation delay other than the rc d elay of the typical on resistance of the switch and the 50 pf load capacitance, when driven by an ideal voltage source (zero output impedan ce). capacitance (note 8) symbol parameter conditions typ max unit c in control pin input capacitance v cc = 5.0 v 3 pf c i/o a/b port input/output capacitance v cc , oe = 5.0 v 5 pf 8. t a = 25 c, f = 1 mhz, capacitance is characterized but not tested.
74fst6800 http://onsemi.com 4 v i v ol v ol + 0.3 v t plh t plh v ol v oh v oh ? 0.3 v t phzl t f = 2.5 ns 90 % 1.5 v 10 % 10 % 1.5 v 90 % t f = 2.5 ns t pzl t pzl output 1.5 v output 1.5 v gnd 3.0 v t pzh enable input t f = 2.5 ns 90 % 1.5 v 1.5 v 90 % 10 % 10 % 1.5 v 1.5 v v oh gnd 3.0 v switch input t f = 2.5 ns c l * from output under test figure 3. ac test circuit figure 4. propagation delays ac loading and waveforms notes: 1. input driven by 50 source terminated in 50 . 2. cl includes load and stray capacitance. *c l = 50 pf 500 500 figure 5. enable/disable delays output
74fst6800 http://onsemi.com 5 package dimensions soic ? 24 d suffix case 751e ? 04 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. ? a ? ? b ? p 12x d 24x 12 13 24 1 m 0.010 (0.25) b m s a m 0.010 (0.25) b s t ? t ? g 22x seating plane k c r x 45 m f j dim min max min max inches millimeters a 15.25 15.54 0.601 0.612 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.41 0.90 0.016 0.035 g 1.27 bsc 0.050 bsc j 0.23 0.32 0.009 0.013 k 0.13 0.29 0.005 0.011 m 0 8 0 8 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 tssop ? 24 dt suffix case 948h ? 01 issue a dim min max min max inches millimeters a 7.70 7.90 0.303 0.311 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ? u ? seating plane 0.10 (0.004) ? t ? ??? ??? section n ? n detail e j j1 k k1 ? w ? 0.25 (0.010) 13 24 12 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ? v ? 24x ref k n n
74fst6800 http://onsemi.com 6 package dimensions qsop ? 24 qs suffix case 492b ? 01 issue o min millimeters g r ? b ? ? a ? l m 0.25 (0.010) t u ? t ? seating plane k d 24 pl c m 0.25 (0.010) t ba s s v n m f 8 pl detail e detail e h x 45 rad. mold pin dim max min max inches a 8.56 8.74 0.337 0.344 b 3.81 3.99 0.150 0.157 c 1.55 1.73 0.061 0.068 d 0.20 0.31 0.008 0.012 f 0.41 0.89 0.016 0.035 g 0.64 bsc 0.025 bsc h 0.20 0.46 0.008 0.018 j 0.249 0.191 0.0098 0.0075 k 0.10 0.25 0.004 0.010 l 5.84 6.20 0.230 0.244 m 0 8 0 8 n 0 7 0 7 p 0.69 0.94 0.027 0.037 q 0.89 dia 0.035 dia r 0.89 1.14 0.035 0.045 u 0.89 1.14 0.035 0.045 v notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. the bottom package shall be bigger than the top package by 4 mils (note: lead side only). bottom package dimension shall follow the dimension stated in this drawing. 4. plastic dimensions does not include mold flash or protrusions. mold flash or protrusions shall not exceed 6 mils per side. 5. bottom ejector pin will include the country of origin (coo) and mold cavity i.d. 0 8 0 8 mark q p 0.013 x 0.005 dp. max rad. 0.005 ? 0.010 typ j on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 74fst6800/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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